Hardware - Verilog - 智能硬件 - Trending Projects

一个从零开始写的极简、非常易懂的RISC-V处理器核。

28天前

从零写一个16位处理器，采用自主设计的大黄鸭指令集，单周期3级流水线，8位指令双发射。配套大黄鸭汇编器，简化程序开发。目前主体设计已完成，大家的支持是我前进的动力。

1年多前

基于zynq的VGA驱动,开发环境：Miz702开发板（兼容zedboard），vivado 2015.2 1.480*640 分辨率 2.显示静态彩色图片

8年多前

Ethernet interfacing and packet processing on FPGAs, starting from a minimum functionality MAC layer design.

6年多前

基于zynq的HDMI驱动,开发环境：Miz702开发板（兼容zedboard），vivado 2015.2

8年多前

Chinese/English Segmenter	Payment Dev	Security Dev	Common Toolkit
Excel Toolkit	Barcode/QRCode	Template Engine	Desktop UI
Network Development Package	Audio Process	Network Tool	Network Service
Data Mining	Job/Task Scheduling	Programming Language/Scripting Language	Cache
Markdown Tools	Search Engine	Microservice	Workflow
Chart/Diagram Component	Authority Management	Reporting Tool	Code Generator
IoC/AOP Framework	Image Library	Rule Engine	JSON Toolkit
Log Toolkit	Spring Boot Extension	Verification Code	Algorithm/Mathematical Calculation
Node Extension	Process Engine	Animation Development	3G/4G/5G

Artificial Intelligence	VR/AR
Machine Learning/Deep Learning	Computer Vision/Face Recognition
Natural Language Processing	LLM

Wechat Development Package	WeChat Applet/Game
WeChat Application	WeChat Game